FPGA Debugging with the 7-Segment Display

When you test your SystemVerilog code on the robot, it is difficult to see what happens inside the FPGA. To debug signals during a test on the robot you can assign these signals to the LEDs on the Basys3 board. However, it can sometimes be more convenient to display the hexadeximal representation of a binary vector on the 7-segment display.

The SystemVerilog code below describes a module that displays digits on the 7-segment display of the Basys3 FPGA board on the robot. It takes the hexadecimal representation of the bit vector on the port digits and it generates the signals to drive the cathodes and anodes of the 7-segment LEDs such that the hexadecimal representation is shown on the display.

module seg7 (
    input  logic clk, rst,
    input  logic [15:0] digits,       // If you assign 16'h1234 the 7-segment display will show 1234. This works the same for any 4-digit hexadecimal value.
    input  logic [3:0] digits_period, // If you assign  4'b1010 the period LED (in the bottom-right for each digit) of digit 3 (leftmost) and 1 (second from the right) will turn on.
    output logic [7:0] ca,
    output logic [3:0] an
);

logic [18:0] count;
logic [1:0] sel;
logic [3:0] [3:0] digits_packed;
logic [3:0] digit_sel;

assign digits_packed = digits;

always_ff @(posedge clk) begin
    count <= count + 1;
end

assign sel = count[18:17];
always_comb
    for (int i = 0; i < 4; i++)
        an[i] = !(sel == i[1:0]);

assign digit_sel = digits_packed[sel];
assign ca[0] = ~digits_period[sel];
always_comb begin
    case (digit_sel)
        4'h0: ca[7:1] = 7'b0000001;
        4'h1: ca[7:1] = 7'b1001111;
        4'h2: ca[7:1] = 7'b0010010;
        4'h3: ca[7:1] = 7'b0000110;
        4'h4: ca[7:1] = 7'b1001100;
        4'h5: ca[7:1] = 7'b0100100;
        4'h6: ca[7:1] = 7'b0100000;
        4'h7: ca[7:1] = 7'b0001111;
        4'h8: ca[7:1] = 7'b0000000;
        4'h9: ca[7:1] = 7'b0000100;
        4'hA: ca[7:1] = 7'b0001000;
        4'hB: ca[7:1] = 7'b1100000;
        4'hC: ca[7:1] = 7'b0110001;
        4'hD: ca[7:1] = 7'b1000010;
        4'hE: ca[7:1] = 7'b0110000;
        4'hF: ca[7:1] = 7'b0111000;
    endcase
end

endmodule

The ports of the 7-segment display can be assigned to the pins of the FPGA in the constaints file as follows.

set_property PACKAGE_PIN W7 [get_ports {ca[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ca[7]}]
set_property PACKAGE_PIN W6 [get_ports {ca[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ca[6]}]
set_property PACKAGE_PIN U8 [get_ports {ca[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ca[5]}]
set_property PACKAGE_PIN V8 [get_ports {ca[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ca[4]}]
set_property PACKAGE_PIN U5 [get_ports {ca[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ca[3]}]
set_property PACKAGE_PIN V5 [get_ports {ca[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ca[2]}]
set_property PACKAGE_PIN U7 [get_ports {ca[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ca[1]}]

set_property PACKAGE_PIN V7 [get_ports ca[0]]
set_property IOSTANDARD LVCMOS33 [get_ports ca[0]]

set_property PACKAGE_PIN U2 [get_ports {an[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property PACKAGE_PIN V4 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]